Research
Reconfigurable CMP Architectures
Recent trends in processor design have been towards including multiple
cores on a single die. The best way to organize these chip
multiprocessors (CMPs) remains an open question. On interesting option
is to include a reconfigurable fabric on die that can dynamically
create the functionality best suited to the running application. A
number of designs have been proposed in the past for single core
systems. The power and area costs of most of these designs have been
prohibitive and so have generally not been adopted in main stream
general purpose processors. With the advent of CMPs, a single fabric
can be shared among multiple cores, amortizing the area and power
costs of the fabric while also increasing the overall utilization of
the fabric. My research focuses on a number of aspects related to
shared reconfigurable fabrics, including the best organization for
such designs, thread scheduling for shared fabrics, and unique uses of
reconfigurable fabrics relative to parallel applications.
On-chip Optical Interconnects
As technology continues to scale, the delay of on-chip wires relative
to logic gates continues to increase. Efficient communication between
cores on a die will be critical to getting the most performance out of
future CMPs. Optical interconnects provide one possible solution to
this problem as they provide lower latency and higher bandwidth
communication than their electrical counterparts. Optical
interconnects also face a number of design and fabrication
limitations. We look at the best way to use optics on-chip given
these features and restrictions.
