Recent papers, please respect all copyrights when viewing published material.
1. M. Bhadauria, V. Weaver, S.A. McKee, "PARSEC: Hardware Profiling for CMP Design", Poster at International Conference on Supercomputing, Yorktown Heights, NY, June, 2009 Extended Abstract
2. K. Singh, M.Bhadauria, S.A. McKee, "Prediction-based Power Estimation and Scheduling for CMPs", Poster at International Conference on Supercomputing, Yorktown Heights, NY, June, 2009 Extended Abstract
3. M. Bhadauria, V. Weaver, S.A. McKee, "Accommodating Diversity in CMPs with Heterogeneous Frequencies", HiPEAC International Conference on High Performance Embedded Architectures and Compilers, Cyprus, January, 2009 Paper
4. K. Singh, M. Bhadauria, S.A. McKee, .Real Time Power Estimation and Thread Scheduling via Performance Counters., Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, at MICRO-41, Italy, November, 2008 Paper
5. M. Bhadauria, S.A. McKee, . Optimizing Thread Throughput for Multithreaded Workloads on Memory Constrained CMPs., ACM International Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008. pp 119-128 Paper
6. Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems M. Bhadauria, S.A. McKee, K. Singh, G. Tyson Proc. International Conference on High Performance Embedded Architectures and Compilers, Ghent, BE, February 2007. Paper
7. A Precisely Tunable Drowsy Cache Management Mechanism M. Bhadauria, S.A. McKee, K. Singh, G. Tyson Proc. Watson Conference on Interaction between Architecture, Circuits, and Compilers(P=AC^2), Yorktown Heights, NY, October 2006.
8. Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems M. Bhadauria, S.A. McKee, K. Singh, G.S. Tyson Transactions on High Performance Embedded Architectures and Compilers (HiPEAC), vol 2. no. 1, 2007, pages 62-81. Paper