office: 471-B Rhodes Hall, Ithaca, NY 14853
email: clt67 at cornell edu
I am a sixth-year PhD student in electrical and computer engineering working under Professor Christopher Batten at Cornell University. My research lies primarily in computer architecture, but I focus on pursuing research that spans across computer architecture and VLSI.
Power and performance are first-order design constraints that dictate the limits of small embedded systems as well as large datacenters. These design considerations span the layers of the computing stack, but research is typically only done within the boundaries of a single layer of expertise. My long-term research vision is to explore how to extract system-level benefit from a cohesive view of circuits, VLSI, and architecture. I significantly value the experience of building real chips, so my research vision also includes space for small research prototypes.
My proposed thesis explores energy-efficient heterogeneous systems of little cores, big cores, and coprocessor-style accelerators, together with a flavoring of ASIC prototyping. My recent research projects have included: Asymmetry-Aware Work-Stealing Runtimes (2015 - 2016) and Reconfigurable Power Distribution Networks (2012 - 2014). I was also the Cornell lead for the design of the Celerity SoC (2017) in TSMC 16nm, which leveraged my previous experience as the project lead for the BRGTC1 (2016) test chip in IBM 130nm.
Energy-Efficient Computer Architecture, Heterogeneous Systems (little cores, big cores, accelerators), Specialized Hardware Accelerators, ASIC Prototyping
Test Chips and Prototyping
- Cornell Lead for the Celerity system-on-chip tapeout (2017) -- Celerity (site) is a 5x5mm 385M-transistor chip in TSMC 16nm designed and implemented by a large team of over 20 students and faculty from UC San Diego, University of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator, manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect, high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Cornell led the Rocket+BNN accelerator logical/physical design and also made key contributions to the top-level logical/physical integration and design/verification methodology.
- Project Lead for the BRGTC1 test chip tapeout (2016) -- BRGTC1 (image) is the BRG research group's first computer architecture test chip. It is a 2x2mm 1.3M-transistor chip in IBM 130nm designed and implemented using our new PyMTL hardware modeling framework. The chip includes a simple pipelined 32-bit RISC processor, custom LVDS clock receiver, 16KB of on-chip SRAM, and application-specific accelerators generated using commercial C-to-RTL high-level synthesis tools. Other students who worked on this project: Moyang Wang (co-lead), Bharath Sudheendra and Nagaraj Murali (physical design), Suren Jayasuriya and Robin Ying (full-custom design), Shreesha Srinath (accelerator design), Mark Buckler (toolflow), and Taylor Pritchard (FPGA emulation).
- Support Designer for the DCS analog test chip (2014) -- DCS is an acronym that stands for dynamic capacitance sharing, a novel circuits technique for dynamically sharing small units of capacitance across multiple on-chip switched-capacitor voltage regulators for significantly reduced on-chip area and order-of-magnitude faster voltage transition times. The DCS analog test chip features four monolithically integrated switched-capacitor DC-DC converters in 65-nm CMOS. As a young PhD student, I hand-designed the digital configuration components in Cadence Virtuoso while adhering to a traditional track-based organization and also supported the post-silicon validation. The project was in collaboration between Professor Christopher Batten and Professor Alyssa Apsel. The chip design was led by Waclaw Godycki and Ivan Bukreyev, resulting in a circuits journal paper (TCAS'17). I co-led an architecture conference paper (MICRO'14) exploring the architectural applications of the technique.
- Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, and Michael B. Taylor. "The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips". IEEE Micro, 38(2):30–41, Mar/Apr. 2018. (special issue for top picks from HOTCHIPS-29) [link,pdf]
- Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer. "A Modular Digital VLSI Flow for High-Productivity SoC Design". 55th ACM/IEEE Design Automation Conference (DAC-55). San Francisco, CA. June 2018. [pdf]
- Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, and Alyssa Apsel. "Four Monolithically Integrated Switched-Capacitor DC-DC Converters with Dynamic Capacitance Sharing in 65-nm CMOS". IEEE Transactions on Circuits and Systems I (TCAS-I), PP(99):1-13. November 2017. [link,pdf]
- Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten. "Using Intra-Core Loop-Task Accelerators to Improve the Productivity and Performance of Task-Based Parallel Programs". 50th IEEE/ACM Int'l Symposium on Microarchitecture (MICRO-50). Boston, MA. October 2017. [link,pdf,slides,poster,video]
- Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, Zhiru Zhang. "Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm". First Workshop on Computer Architecture Research with RISC-V (CARRV 2017). Boston, MA. October 2017. [pdf,slides,site]
- Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, Zhiru Zhang. "Celerity: An Open Source RISC-V Tiered Accelerator Fabric". 29th Symposium on High Performance Chips (HotChips-29). Cupertino, CA. August 2017. [slides,site]
- Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, and Christopher Batten. "Experiences Using A Novel Python-Based Hardware Modeling Framework For Computer Architecture Test Chips". Poster at the 28th Symposium on High Performance Chips (HotChips-28). Cupertino, CA. August 2016. [pdf,slides,poster]
- Christopher Torng, Moyang Wang, and Christopher Batten. "Asymmetry-Aware Work-Stealing Runtimes". 43rd ACM/IEEE Int'l Symp. on Computer Architecture (ISCA-43). Seoul, Korea. June 2016. [pdf,slides,errata]
- Waclaw Godycki, Christopher Torng (co-lead), Ivan Bukreyev, Alyssa Apsel, and Christopher Batten. "Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks". 47th IEEE/ACM Int'l Symposium on Microarchitecture (MICRO-47). Cambridge, UK. December 2014. [pdf,slides]
- Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, and Christopher Batten. "Microarchitectural Mechanisms to Exploit Value Structure in SIMT Architectures". 40th ACM/IEEE Int'l Symposium on Computer Architecture (ISCA-40). Tel Aviv, Israel. June 2013. [pdf]
- Christopher Torng. "Towards Rapid Chip Development with Celerity and BRGTC1". Presented at the Computer Architecture Lab at Carnegie Mellon. Pittsburgh, PA. April 2018.
- Christopher Torng, Tutu Ajayi, and Shaolin Xie. "Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm". Presented at the First Workshop on Computer Architecture Research with RISC-V (CARRV 2017). Boston, MA. October 2017.
- Christopher Torng, Khalid Al-Hawaj, and Ritchie Zhao. "Celerity: An Open Source RISC-V Tiered Accelerator Fabric". Presented at the Cornell Electron Devices Society (EDS). Ithaca, NY. September 2017.
- Christopher Torng. "Asymmetry-Aware Work-Stealing Runtimes". Presented at the 43rd ACM/IEEE Int'l Symp. on Computer Architecture (ISCA-43). Seoul, Korea. June 2016.
- Christopher Torng and Waclaw Godycki. "Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks". Presented at the 47th IEEE/ACM Int'l Symposium on Microarchitecture (MICRO-47). Cambridge, UK. December 2014.
- Christopher Torng and Waclaw Godycki. "Reconfigurable Power Distribution Networks for Embedded Multicore Processors". Presented at the Qualcomm Innovation Fellowship Finals. Bridgewater, NJ. March 2013.
- Christopher Torng. "On-Chip Reconfigurable Power Distribution Networks". Presented to non-experts at the Cornell STEM Graduate Student Summer Colloquium. Ithaca, NY. July 2013.
- Lead Graduate TA - ECE 2400 / ENGRD 2140 Computer Systems Programming - Fall 2017
- Lead Graduate TA - ECE 4750 / CS 4420 Computer Architecture - Fall 2014
- Lead Graduate TA - CURIE Academy - Summer 2014 - Educational outreach program for high school girls focusing on exploring STEM fields and taking a special, deep dive into computer engineering [link]
- Graduate TA - ENGRG 1060 Exploration in Engineering Seminar - Summer 2013 - Educational outreach targeted at introducing high school students to STEM fields through an Arduino-based robotics lab
- Undergraduate TA - ECE 4750 / CS 4420 Computer Architecture - Fall 2011
- Graduate Research Intern - NVIDIA ASIC/VLSI Research Group - Austin, TX, USA - Summer 2017
- Graduate Technical Intern - Intel Many Integrated Core (MIC) - Hillsboro, OR, USA - Summer 2012
- Undergraduate Technical Intern - Intel Many Integrated Core (MIC) - Hillsboro, OR, USA - Summer 2011
- NSF GRFP Honorable Mention 2014
- Finalist for Qualcomm Innovation Fellowship (QInF) 2013
- H.C. Torng Fellowship 2012 (Cornell one-semester graduate fellowship) (no familial relation)
- Conference Shadow PC Member: ASPLOS 2018
- Journal Reviewer: IEEE TCAS-I 2016
Light Contributions to Open Source Projects
- gem5: [small feature] Enabled fast-forwarding for MIPS inorder and out-of-order cores in The gem5 Simulator System - Spring 2014 [link]
- gem5: [small feature] Added support for dynamic frequency scaling in single core and multicore architectures in The gem5 Simulator System - Fall 2013 [link]
- gem5: [bug fix] Fixed floating point convert instruction signedness bug for MIPS architectures in The gem5 Simulator System - Fall 2013 [link]