Christopher Torng

Ph.D. Candidate

I am applying for faculty positions in electrical engineering and computer science for the 2018-2019 hiring season.

Application Materials: - Research - Teaching - CV - Job Talk Slides -

Computer Systems Laboratory
School of Electrical and Computer Engineering
Cornell University

office: 471-B Rhodes Hall, Ithaca, NY 14853
email: clt67 at cornell edu

I am a final-year PhD student in electrical and computer engineering working under Professor Christopher Batten at Cornell University. I am a computer architect, but my research approach emphasizes cross-stack co-design across software, architecture, and VLSI to unify emerging applications with emerging technologies.

Throughout my PhD, I have been involved with six research test chips that support my research, and I was the project lead or university student lead for three of the chips including BRGTC2 (2018), Celerity (2017), and BRGTC1 (2016). My activities have resulted in a selection as a Rising Star in Computer Architecture (2018) by Georgia Tech and an IEEE MICRO Top Pick from Hot Chips (2018).

In the future, I plan to co-design across software, architecture, and VLSI (1) to build new accelerator-centric SoCs that enable new applications based on intelligence on the edge, (2) to explore new accelerator-centric SoCs that are easy to build using novel methodologies supporting a tile-based abstraction, and (3) to build new SoCs that can be embedded into cyber-physical systems.

Research Projects

Efficient Task-Based Parallel Runtimes

Task-based parallel runtimes underpin the parallelization of frameworks for machine learning, graph analytics, and other domains. State-of-the-art graph analytics frameworks like GraphIt and Ligra are designed on top of these runtimes to enable efficient task distribution using dynamic work-stealing algorithms. A cross-stack research approach can expose runtime-level information to hardware to influence both architecture-level and VLSI-level decisions to improve performance and energy efficiency of the runtime (ISCA'16). However, walls of abstraction often make it challenging to pass information through layers of the computing stack. I worked on a systematic approach to convey the abstraction of a "task" from the runtime directly to the underlying hardware (MICRO'17). I designed and fabricated BRGTC2, a 6.7M-transistor chip in TSMC 28nm, to collect performance, area, and energy numbers in an advanced technology node to support future research projects based on hardware acceleration for task-based parallel runtimes (RISCV'18).


BRGTC2 (2018)

Integrated Voltage Regulation

Voltage regulators are responsible for efficiently converting one voltage level into another (e.g., board-level to chip-level). Recent technology trends are making it feasible to replace discrete voltage regulators with integrated voltage regulators, which can significantly reduce system cost by eliminating expensive board-level components. The enabling trends include energy storage elements with better energy densities as well as faster on-chip switches with lower parasitic losses. However, integrated voltage regulators are very large (e.g., similar area as the core it supplies). Together with my colleagues in the circuits field, I applied a cross-stack research approach to explore a novel technique that dynamically shares capacitance across multiple loads for a 40% reduction in regulator area while still enabling fine-grain DVFS (MICRO'14). I also contributed to the fabrication of a switched-capacitor-based prototype in 65nm CMOS resulting in a journal publication in a top-tier circuits venue (TCASI'18).


DCS (2014)

Rapid ASIC Design

Rising SoC design costs have created a formidable barrier to hardware design when using traditional design tools and methodologies. It is exceedingly difficult for small teams with a limited workforce to build meaningfully complex chips for business ventures (e.g., chip-based startups in machine learning), in academia (i.e., research groups), and even for government goals (e.g., U.S. Department of Defense). I have been involved in a range of efforts to reduce the costs and challenges of ASIC design for small teams based on productive toolflows and open-source hardware. I was the Cornell University student lead on the Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric resulting in top-tier publications in chip-design venues (HOTCHIPS'17), architecture venues (IEEE-MICRO'18), and various workshops. I was also the project lead for BRGTC1 and BRGTC2, which are silicon prototypes in IBM 130nm and TSMC 28nm designed and implemented using a new open-source Python-based hardware modeling framework called PyMTL developed by my research group. Finally, I contributed to an effort at NVIDIA Research on a modular digital VLSI flow for high-productivity SoC design based on high-level synthesis tools (DAC'18).


Celerity (2017)

Research


Top-tier architecture venues in this list

IEEE MICRO, ISCA, MICRO

Top-tier chip / design automation venues in this list

HotChips, DAC

Top-tier circuits venues in this list

IEEE TCAS I


Additional Talks and Research Presentations

Awards

Media Coverage

Test Chips and Prototyping

Teaching Experience

Industry Experience

Professional Activities

My Open-Source Projects

Other Light Contributions to Open-Source Projects

Fun Activities