office: 471-B Rhodes Hall, Ithaca, NY 14853
email: clt67 at cornell edu
I am a final-year PhD student in electrical and computer engineering working under Professor Christopher Batten at Cornell University. My research lies primarily in computer architecture, but my research approach also focuses on tying computer architecture up to software and down to VLSI.
My research on software-defined hardware specialization focuses on creating system architectures that specialize for productive software domains and yet leverage novel circuits techniques. I am also interested in the challenge of enabling rapid ASIC development and building open-source hardware. Throughout my PhD, I have built a total of six research test chips, and I was the project lead / university student lead for three of the chips including BRGTC2 (2018), Celerity (2017), and BRGTC1 (2016).
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric:
Fast Architectures and Design Methodologies for Fast Chips
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, and Michael B. Taylor
IEEE Micro 2018: 38(2):30–41, Mar/Apr. 2018. Special issue for top picks from HOTCHIPS-29.
A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer
DAC 2018: 55th ACM/IEEE Design Automation Conference. San Francisco, CA. June 2018.
- Paper -
Four Monolithically Integrated Switched-Capacitor DC-DC Converters
with Dynamic Capacitance Sharing in 65-nm CMOS
Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, and Alyssa Apsel
TCAS 2017: IEEE Transactions on Circuits and Systems I (TCAS-I), PP(99):1-13. November 2017.
Using Intra-Core Loop-Task Accelerators to Improve the
Productivity and Performance of Task-Based Parallel Programs
Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten
MICRO 2017: 50th IEEE/ACM Int'l Symposium on Microarchitecture. Boston, MA. October 2017.
Experiences Using the RISC-V Ecosystem to Design an
Accelerator-Centric SoC in TSMC 16nm
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, Zhiru Zhang
CARRV 2017: First Workshop on Computer Architecture Research with RISC-V. Boston, MA. October 2017.
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, Zhiru Zhang
HotChips 2017: 29th Symposium on High Performance Chips. Cupertino, CA. August 2017.
Experiences Using A Novel Python-Based Hardware Modeling Framework
For Computer Architecture Test Chips
Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, and Christopher Batten
Poster at HotChips 2016: 28th Symposium on High Performance Chips. Cupertino, CA. August 2016.
Asymmetry-Aware Work-Stealing Runtimes
Christopher Torng, Moyang Wang, and Christopher Batten
ISCA 2016: 43rd ACM/IEEE Int'l Symp. on Computer Architecture. Seoul, Korea. June 2016.
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable
Power Distribution Networks
Waclaw Godycki, (paper co-lead) Christopher Torng, Ivan Bukreyev, Alyssa Apsel, and Christopher Batten
MICRO 2014: 47th IEEE/ACM Int'l Symposium on Microarchitecture. Cambridge, UK. December 2014.
Microarchitectural Mechanisms to Exploit Value Structure in SIMT
Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, and Christopher Batten
ISCA 2013: 40th ACM/IEEE Int'l Symposium on Computer Architecture. Tel Aviv, Israel. June 2013.
- Paper -
Additional Talks and Research Presentations
- Towards Rapid Chip Development with Celerity and BRGTC1 [abstract]
CMU Computer Architecture Lab (CALCM). Pittsburgh, PA. April 2018.
- Celerity: An Open Source RISC-V Tiered Accelerator Fabric
Cornell Electron Devices Society. Ithaca, NY. September 2017. Presented with Khalid Al-Hawaj and Ritchie Zhao.
- Reconfigurable Power Distribution Networks for Embedded Multicore
Qualcomm Innovation Fellowship Finals (QInF 2013). Bridgewater, NJ. March 2013. Presented with Waclaw Godycki.
- On-Chip Reconfigurable Power Distribution Networks
Cornell STEM Graduate Student Summer Colloquium. Ithaca, NY. July 2013. Presented to about fifty audience who were non-experts.
Test Chips and Prototyping
Project Lead for the BRGTC2 test chip (2018)
BRGTC2 is the BRG research group's second computer architecture test chip. It is a 1x1.25mm 6.7M-transistor chip in TSMC 28nm designed and implemented using our new PyMTL hardware modeling framework. The chip includes four RISC-V RV32IMAF cores which share a 32KB instruction cache, 32KB data cache, and single-precision floating point unit along with microarchitectural mechanisms to mitigate the performance impact of resource sharing. The chip also includes a fully synthesizable high-performance PLL originally designed for the DARPA CRAFT project by Ian Galton and Julian Puscar from UC San Diego. Project was led by Christopher Torng with contributions from Shunning Jiang (core RTL design, verification), Khalid Al-Hawaj (cache RTL design, verification), Ivan Bukreyev (PLL porting), Berkin Ilbeyi (Bloom filter and FPU design), Tuan Ta (CL simulation, arbiter RTL design), and Lin Cheng (microbenchmark development).
Cornell Lead for the Celerity system-on-chip
(annotated chip plot,
Celerity is a 5x5mm 385M-transistor chip in TSMC 16nm designed and implemented by a large team of over 20 students and faculty from UC San Diego, University of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator, manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect, high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Cornell led the Rocket+BNN accelerator logical/physical design and also made key contributions to the top-level logical/physical integration and design/verification methodology.
Project Lead for the BRGTC1 test chip
(annotated chip plot,
BRGTC1 is the BRG research group's first computer architecture test chip. It is a 2x2mm 1.3M-transistor chip in IBM 130nm designed and implemented using our new PyMTL hardware modeling framework. The chip includes a simple pipelined 32-bit RISC processor, custom LVDS clock receiver, 16KB of on-chip SRAM, and application-specific accelerators generated using commercial C-to-RTL high-level synthesis tools. Other students who worked on this project: Moyang Wang (co-lead), Bharath Sudheendra and Nagaraj Murali (physical design), Suren Jayasuriya and Robin Ying (full-custom design), Shreesha Srinath (accelerator design), Mark Buckler (toolflow), and Taylor Pritchard (FPGA emulation).
Support Designer for the DCS analog test chip
(annotated chip plot)
DCS is an acronym that stands for dynamic capacitance sharing, a novel circuits technique for dynamically sharing small units of capacitance across multiple on-chip switched-capacitor voltage regulators for significantly reduced on-chip area and order-of-magnitude faster voltage transition times. The DCS analog test chip features four monolithically integrated switched-capacitor DC-DC converters in 65-nm CMOS. As a young PhD student, I hand-designed the digital configuration components in Cadence Virtuoso while adhering to a traditional track-based organization and also supported the post-silicon validation. The project was in collaboration between Professor Christopher Batten and Professor Alyssa Apsel. The chip design was led by Waclaw Godycki and Ivan Bukreyev, resulting in a circuits journal paper (TCAS'17). I co-led an architecture conference paper (MICRO'14) exploring the architectural applications of the technique.
- (Lead) Teaching Assistant - ECE 2400 / ENGRD 2140 Computer Systems Programming - Fall 2017
- (Lead) Teaching Assistant - ECE 4750 / CS 4420 Computer Architecture - Fall 2014
- (Lead) Teaching Assistant - CURIE Academy - Summer 2014 - Educational outreach program for high school girls focusing on exploring STEM fields and taking a special, deep dive into computer engineering
- Teaching Assistant - ENGRG 1060 Exploration in Engineering Seminar - Summer 2013 - Educational outreach targeted at introducing high school students to STEM fields through an Arduino-based robotics lab
- Undergraduate Teaching Assistant - ECE 4750 / CS 4420 Computer Architecture - Fall 2011
- Graduate Research Intern - NVIDIA ASIC/VLSI Research Group - Austin, TX, USA - Summer 2017
- Graduate Technical Intern - Intel Many Integrated Core (MIC) - Hillsboro, OR, USA - Summer 2012
- Undergraduate Technical Intern - Intel Many Integrated Core (MIC) - Hillsboro, OR, USA - Summer 2011
- NSF GRFP Honorable Mention 2014
- Finalist for Qualcomm Innovation Fellowship (QInF) 2013
- H.C. Torng Fellowship 2012 (Cornell one-semester graduate fellowship) (no familial relation)
- Conference Shadow PC Member: ASPLOS 2018
- Journal Reviewer: IEEE TCAS-I 2016
Light Contributions to Open Source Projects
- gem5: [small feature] Enabled fast-forwarding for MIPS inorder and out-of-order cores in The gem5 Simulator System - Spring 2014 [link]
- gem5: [small feature] Added support for dynamic frequency scaling in single core and multicore architectures in The gem5 Simulator System - Fall 2013 [link]
- gem5: [bug fix] Fixed floating point convert instruction signedness bug for MIPS architectures in The gem5 Simulator System - Fall 2013 [link]