The High-Performance Microprocessor Systems Group researches architecture and code optimization techniques to improve the performance, reduce the complexity, and decrease the power consumption of sequential and parallel computers.

Overview

The driving factor behind the microprocessor revolution has been the exponential growth in performance. Architecture and code optimizations have substantially contributed to this rapid progression, but the most important aspect was the tremendous increase in clock frequency. However, we have reached an inflection point where power consumption and complexity issues prevent significant further speedup of the clock frequency. Hence, we urgently need to develop ways to reduce the energy needs, simplify, and accelerate computers. If we fail to do so, processors will not be able to keep up with the rapidly increasing software demands and the quickly growing data set sizes. This will not only stifle the hardware and software domains but also the progress of our technology-driven society as a whole, which heavily depends on advances in computing capabilities. Architecture and code optimizations are the primary areas of research for overcoming these challenges.

For many years, the computation speed has been increasing more rapidly than the speed at which data can be retrieved, largely because the amount of data has grown drastically. Since enlarging the capacity of memory and storage devices makes them slower and our desire for more and more data is unlikely to diminish, this performance gap is bound to become wider. Industry's recent move towards placing multiple processors on a single chip only exacerbates the situation because the processors compete for the same memory. As a result, much of the computation capabilities of a modern CPU are never realized since the CPU often has to wait for the rest of the system to supply the data, even though high-end designs already dedicate two thirds of the chip area to accelerating the delivery of data.

The goal of our research is to make computers more energy efficient, less complex, and faster by alleviating and exploiting this imbalance between processing power and data access speed. Thus, we have invented simple yet very effective hardware approaches to minimize and tolerate slow data accesses, we have devised high-throughput compression algorithms to reduce the amount of data that needs to be transferred and stored, and we have created innovative software techniques to request data early and hide the data access latency.