Workshop on Complexity-Effective Design
June 18, 2006
Boston, Massachusetts
To be held in conjunction with the 33rd International Symposium on Computer
Architecture (ISCA-33)
Proceedings
Program
Prior WCEDs
Panel Information
Title: An Agenda for Computer Architecture Research on Hardware Complexity
Moderator: Josep Torrellas, University of Illinois (Introduction, Conclusions)
Panelists:
- Dennis Abts, Cray (Slides)
- Dan Leibholz, AMD (Slides)
- Jose Renau, University of California, Santa Cruz (Slides)
- John Shen, Intel (Slides)
- Victor Zyuban, IBM (Slides)
Organizers:
David H. Albonesi
Cornell University
albonesi@csl.cornell.edu
Pradip Bose
IBM T. J. Watson Research Center
pbose@us.ibm.com
Prabhakar Kudva
IBM T. J. Watson Research Center
kudva@us.ibm.com
Diana Marculescu
Carnegie-Mellon University
dianam@ece.cmu.edu
Motivation: The quest for higher performance via deep
pipelining, speculative and multi-threaded execution, and
chip-multiprocessing, has yielded microprocessors with greater
performance, but at the expense of greater design complexity. The
costs of higher complexity are many-fold, including increased
verification time, higher power dissipation, and reduced scalability
with microarchitectural resource size parameters and process
shrinks. The goal of this workshop is to provide a forum for
microarchitects, circuit designers, performance modelers, compiler
developers, verification experts, and system designers to discuss and
explore hardware/software techniques and tools for creating future
designs that are more complexity-effective
(CE).
Topics of interest:
-
Metrics for establishing the CE of a given design. Scalability
criteria and evaluation. Quantifying verification complexity.
Power-performance metrics.
-
Characterization of current and emerging workloads to help determine
the CE value of alternate design paradigms.
-
Impact of clock- and Vdd-gating on verification and reliability in
power-aware designs.
-
Approaches to improving power-efficiency without unduly increasing
design complexity.
-
Microarchitectures that scale effectively with process
shrinks/variations.
-
Design-for-verification architectures.
-
The merits of different architectural approaches (ooo versus
in-order superscalar, VLIW/EPIC, clustered microarchitectures, chip
multiprocessor, multithreading, multi-clock, GALS, and asynchronous
architectures, etc.) in terms of their CE.
-
Case studies of actual designs in which CE was taken into account.
-
Pipeline depth and CE issues, including "helper" pipeline
approaches.
-
Analytical models for power-performance or performance-verifiability
tradeoffs.
-
Compiler and operating system support for CE, e.g., moving
functionality to software in order to reduce overall design
complexity.
Full conference length papers are fine but not a requirement.
Short idea/position papers addressing one of the above issues are
encouraged. We highly encourage "perspectives" or "real world
experience" articles from industry.
Program Committee:
- Dennis Abts, Cray
- Dave Albonesi, Cornell University
- R. Iris Bahar, Brown University
- Pradip Bose, IBM T.J. Watson
- David Brooks, Harvard University
- Alper Buyuktosunoglu, IBM T.J. Watson
- George Cai, Intel
- Babak Falsafi, Carnegie Mellon University
- Keith Farkas, Hewlett Packard
- Antonio Gonzalez, Intel and UPC
- Peter Hofstee, IBM Austin
- Prabhakar Kudva, IBM T.J. Watson
- Diana Marculescu, Carnegie Mellon University
- Gokhan Memik, Northwestern University
- Chuck Moore, Advanced Micro Devices
- Jose Renau, University of California, Santa Cruz
Schedule:
Submission deadline (extended abstract or full paper in PDF format emailed
to any of the co-chairs): April 19, 2006
Acceptance notification: April 28, 2006
Final version due: May 19, 2006
A post-workshop proceedings, containing abstracts, full papers, and/or
talk slides, will be distributed.