Organizers:
David H. Albonesi
Cornell University
albonesi@csl.cornell.edu

Pradip Bose
IBM T. J. Watson Research Center
pbose@us.ibm.com

Prabhakar Kudva
IBM T. J. Watson Research Center
kudva@us.ibm.com

Diana Marculescu
Carnegie-Mellon University
dianam@ece.cmu.edu

NOTE TO PROSPECTIVE AUTHORS: This year's WCED will only be a half-day workshop. We will be vigilant about accepting only those papers that are focused on the overall workshop themes, i.e., (a) producing a significant performance and/or power efficiency improvement relative to the increase in hardware/software complexity; or (b) significantly reducing complexity with a tolerable performance/power impact. Either full papers or short abstracts are acceptable. We highly encourage "perspectives" or "real world experience" articles from industry.

Motivation: The quest for higher performance via deep pipelining (for high clock rate) and speculative, out-of-order execution (for high IPC) has yielded processors with greater performance, but at the expense of much greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with microarchitectural resource size parameters and process shrinks. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE).

Topics of interest:

• Metrics for establishing the CE of a given design. Scalability criteria and evaluation. Quantifying verification complexity. Power-performance metrics.
• Characterization of current and emerging workloads to help determine the CE value of alternate design paradigms.
• Impact of clock- and Vdd-gating on verification and reliability in power-aware designs.
• Approaches to improving power-efficiency without unduly increasing design complexity.
• Microarchitectures that scale effectively with process shrinks/variations.
• Design-for-verification architectures.
• The merits of different architectural approaches (ooo versus in-order superscalar, VLIW/EPIC, clustered microarchitectures, chip multiprocessor, multithreading, multi-clock, GALS, and asynchronous architectures, etc.) in terms of their CE.
• Case studies of actual designs in which CE was taken into account.
• Pipeline depth and CE issues, including "helper" pipeline approaches.
• Analytical models for power-performance or performance-verifiability tradeoffs.
• Compiler and operating system support for CE, e.g., moving functionality to software in order to reduce overall design complexity.

Full conference length papers are fine but not a requirement. Short idea/position papers addressing one of the above issues are encouraged. We highly encourage "perspectives" or "real world experience" articles from industry.

Program Committee:

• Dave Albonesi, Cornell University
• Todd Austin, University of Michigan
• R. Iris Bahar, Brown University
• Pradip Bose, IBM T.J. Watson
• David Brooks, Harvard University
• Alper Buyuktosunoglu, IBM T.J. Watson
• George Cai, Intel
• Babak Falsafi, Carnegie Mellon University
• Keith Farkas, Hewlett Packard
• Antonio Gonzalez, Universidad Politecnica de Catalunya
• Peter Hofstee, IBM Austin
• Prabhakar Kudva, IBM T.J. Watson
• Diana Marculescu, Carnegie Mellon University
• Gokhan Memik, Northwestern University
• Chuck Moore, Advanced Micro Devices
• Subbarao Palacharla, McDATA Corporation

Schedule:
Submission deadline (extended abstract or full paper in PDF format emailed to any of the co-chairs): April 25, 2005
Acceptance notification: May 4, 2005
Final version due: May 13, 2005

A post-workshop proceedings, containing abstracts, full papers, and/or talk slides, will be distributed.