J.A. Winter and D.H. Albonesi. Scheduling algorithms for unpredictably heterogeneous CMP architectures. In Intl. Conf. on Dependable Systems and Networks (DSN), Anchorage, AK, June 2008

E. İpek, O. Mutlu, J.F. Martínez, and R. Caruana. Self-optimizing memory controllers: A reinforcement learning approach. In Intl. Symp. on Computer Architecture (ISCA), Beijing, China, June 2008

J.A. Winter and D.H. Albonesi. Addressing Thermal Non-Uniformity in SMT Workloads. ACM Trans. on Architecture and Code Optimization (TACO), Vol. X, No. Y, ZZZ. 2008

E. İpek, S.A. McKee, K. Singh, R. Caruana, B.R. de Supinski, and M. Schulz. Efficient architectural design space exploration via predictive modeling. ACM Trans. on Architecture and Code Optimization (TACO), Vol. 4, No. 4, Jan. 2008

G.E. Suh, C.W. O'Donnell, and S. Devadas. AEGIS: A single-chip secure processor. IEEE Design & Test of Computers, Vol.24, No.6, Nov.-Dec. 2007

E. İpek, M. Kırman, N. Kırman, and J.F. Martínez. Core Fusion: Accommodating software diversity in chip multiprocessors. In Intl. Symp. on Computer Architecture (ISCA), San Diego, CA, June 2007

G.E. Suh and S. Devadas. Physical unclonable functions for device authentication and secret key generation (invited paper). In Design Automation Conf. (DAC), San Diego, CA, June 2007

C.C. LaFrieda, E. İpek, J.F. Martínez, and R. Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. In Intl. Conf. on Dependable Systems and Networks (DSN), Edinburgh, Scotland, June 2007

J. Marathe, F. Mueller, T. Mohan, S.A. McKee, B.R. de Supinski, and A. Yoo. METRIC: Memory tracing via dynamic binary rewriting to identify cache inefficiencies. ACM Trans. on Programming Languages and Systems (TOPLAS), Vol. 29, No. 2, April 2007

B.C. Lee, D.M. Brooks, B.R. de Supinski, M. Schulz, K. Singh , and S.A. McKee. Methods of inference and learning for performance modeling of parallel applications. In Symp. on Principles and Practice of Parallel Programming (PPoPP), San Jose, CA, March 2007