Course Overview

• N. Weste and D. Harris. Chapter 1. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ pdf | link ]

Topic 1: Hardware Description Languages

• J. Bromley. Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports. Design and Verification Conference and Exhibition (DVCon), Feb. 2007. [ pdf ]
• J. Hoe and Arvind. Operation-Centric Hardware Description and Synthesis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 23(9):1277–1288, 2004. [ pdf | link ]
• L. Cai and D. Gajski. Transaction-Level Modeling: An Overview. Int'l Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2003. [ pdf | link ]

Topic 2: CMOS Devices

• N. Weste and D. Harris. Chapters 2–3. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]
• L. Gwennap. Foundries Head to 5nm and Beyond. Microprocessor Report, Aug. 2018. [ pdf ]
• L. Gwennap. GlobalFoundries' New Strategy. Microprocessor Report, Aug. 2018. [ pdf ]

Topic 3: CMOS Circuits

• N. Weste and D. Harris. Chapters 1.9. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 4: Full-Custom Design Methodology

• N. Weste and D. Harris. Chapter 14.1–2. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 5: Automated Design Methodologies

• N. Weste and D. Harris. Chapter 14.3–14.4, 12.7. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 6: Closing the Gap Between ASIC and Custom

• D. Chinnery and K. Keutzer. Chapter 1. Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Springer, 2002. [ pdf | link ]
• D. Chinnery and K. Keutzer. Chapter 2. Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low-Power Design, Springer, 2007. [ pdf | link ]
• W.J. Dally and A. Chang. The Role of Custom Design in ASIC Chips. Design Automation Conf., June 2000. [ pdf | link ]
• A. Chang and W.J. Dally. Explaining the Gap Between ASIC and Custom Power: A Custom Perspective. Design Automation Conf., June 2005. [ pdf | link ]

Topic 7: Packaging, Power Distribution, Clocking, and I/O

• N. Weste and D. Harris. Chapter 13. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 8: Testing and Verification

• N. Weste and D. Harris. Chapter 15. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 9: CMOS Combinational Logic

• N. Weste and D. Harris. Chapters 4–5. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ] (key insights)
• I. Sutherland, B. Sproull, and D. Harris. Chapter 1. Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. [ pdf | link ]

Topic 10: CMOS Sequential State

• N. Weste and D. Harris. Chapters 10.1–10.2. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 11: CMOS Interconnect

• N. Weste and D. Harris. Chapters 6. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison Wesley, 2011. [ link ]

Topic 12: Synthesis Algorithms

• S. Devadas, A. Ghosh, and K. Keutzer. Chapters 4.1–4.2, 4.6, 7.7, 8.6. Logic Synthesis, McGraw-Hill Professional 1994. [ pdf | link ]
• S. Nowick. The Quine-McCluskey Method. Handout from Columbia CSEE E6861y Computer-Aided Design of Digital Systems, 2012. (included with permission) [ pdf ]

Topic 13: Physical Design Automation Algorithms

• A.B. Kahng, J. Liening, I.L. Markov, and J. Hu. Chapters 2.1–2.4.1, 4.1–4.3.2, 5.1–5.6.1, 6.1–6.3.1 . VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer 2011. [ pdf | link ]