image/svg+xml
immgen
[19:15]
[24:20]
ex_result_reg_M
regfile(read)
regfile(write)
alu
wb_result_sel_M
rf_wen_W
rf_waddr_W
Fetch (F)
Decode (D)
Execute (X)
Memory (M)
Writeback (W)
br_target_reg_X
op2_sel_D
reg_en_D
inst_D
reg_en_X
dmemreq_msg_addr
dmemresp_msg_data
reg_en_M
reg_en_W
proc_to_mngr_data
mngr_to_proc_data
pc_sel_F
imemreq_msg_addr
reg_en_F
+4
pc_incr_F
br_target_X
pc_reg_F
pc_sel_mux_F
pc_plus4_F
pc_next_F
pc_reg_D
inst_D_reg
inst_D
rf_rdata0_D
rf_rdata1_D
rf
op2_sel_mux_D
wb_result_sel_mux_M
wb_result_reg_W
rf_wdata_W
pc_F
alu_fn_X
br_cond_eq_X
imemresp_msg_data
+
imm_type_D
csrr_sel_D
csrr_sel_mux_D
num_cores
core_id
pc_plus_imm_D
jalr_target_X
pc_reg_X
op1_reg_X
op2_reg_X
op1_sel_mux_D
op1_sel_D
dmem_write_data_reg_X
dmemreq_msg_data
br_cond_lt_X
br_cond_ltu_X
imul
imul_req_val_D
imul_req_rdy_D
imul_resp_val_X
imul_resp_rdy_X
+4
pc_incr_X
imul_req_msg
ex_result_sel_mux_X
ex_result_sel_X
jal_target_D
rf
imul_resp_msg
wb_result_reg_W
stats_en_wen_W
stats_en
imm_gen_D