Reminder: All layout in this class will use the magic technology file SCN3ME_SUBM.30, which can be specified on the command line by saying: magic -T SCN3ME_SUBM.30. You might want to alias magic to magic -T SCN3ME_SUBM.30 in your .cshrc.

Make sure you read the ENTIRE lab before starting.

• The file lab5.tgz contains a template for the layout for this lab. The top-level mag file is called MyFrame.mag. Spend some time looking at the layout. Each pad has some metal1 on it, which you should label p[0]...p[39] (cell id p0 should have label p[0], etc).
• An InPad has a couple of inverters that connect the piece of metal1 painted on top of the pad to a signal that is made available on the other end of cell (toward the chip interior); an OutPad is similar, except the signal is taken from the chip interior and driven toward the output. These are the signals you will have to connect to. You also have VddPad and GNDPad, both of which are different because they connect the piece of metal1 on them to an entire ring of metal3 passing through all the pads. This means that you can connect to Vdd/GND anywhere on the exterior.

Use the sizing ideas to improve the performance of your design. In particular, we expect to see some clock inverters used to drive the clock signal on-chip. Also, make sure that the outputs of the PLA are staticized.

Testing. We expect a thorough test of your chip. Apart from systematic testing, we also want to see some random testing. For instance, initialize your memory with random values and make sure your chip does "the right thing." (You can assume that unspecified opcodes will not be in the memory.)

README. In addition to the usual information, the README file must also contain a description of the # of cycles it takes your processor to execute an instruction (each instruction type might be different). If your processor overlaps instruction executions, then mention that as well. For instance, you could say "load: 3 cycles + the # of cycles Mdone is high". The file must also contain your cycle time. If your clock is not balanced (i.e. each phase has a different size), please provide your clock and stepsize definition.

Evaluation criteria. You will be graded on

• Correctness of your design (this is basically the lab4 part of the grade)
• Thoroughness of testing
• Clock design (have you optimized the delay from the clock arriving at the pad to the on-chip clock that is connected to latches/precharges on-chip)
• Quality of layout: this primarily refers to floorplanning
• Quality of your design: how efficient is your design in terms of the cycle time, number of cycles to execute an instruction, complexity of your control logic, datapath complexity, etc.

• The lab number and the names of the group members and their CSL login ids.
• A picture of the complete layout for your processor.
• Cycle time estimate for your processor.
• The dimensions of the bounding rectangle for your layout in lambda are unnecessary for this lab, since everyone's layout will be 5000x5000 lambda.

Electronic Submission. Use the CMS system to submit your files electronically. Create a .tar.gz file and submit that file. Make sure that the file contains a plain text README file that documents your submission. As in Lab 1, make sure that the .tar.gz file ONLY contains the files that you wrote; do not include any file that is generated by a tool (e.g., no .ext files, no .trace files, etc etc). Instructions on testing the lab should be contained in the README.