Reminder: All layout in this class will use the magic technology file SCN3ME_SUBM.30, which can be specified on the command line by saying: magic -T SCN3ME_SUBM.30. You might want to alias magic to magic -T SCN3ME_SUBM.30 in your .cshrc.

Make sure you read the ENTIRE lab before starting.

As always, all designs must be accompanied by a CAST file containing the production rules that lvs against the layout.

• bz imm: op=00: If A=0, pc:=pc+sext(imm) where sext sign-extends the 5-bit immediate field.
• bnz imm: op=01: If A!=0, pc:=pc+sext(imm)
• li imm: op=10: A:=sext(imm)
• stpc: op=11: A:=pc

The R-format instructions are as follows:

• Clocks. p[0]: phi0, p[1]: phi1
• Reset. p[2]: reset (active high)
• Power. p[3]: Vdd, p[4]: GND
• ZBus. p[5] ... p[12] should be connected to the "wz" bus after two inverters (lsb should be p[45]). This is for debugging purposes.
• Addr. p[13] .. p[20] are the eight address pins used to access off-chip memory.
• Dout. p[21] .. p[28] is data written out to the data memory (via the store instruction).
• Din. p[29] .. p[36] is data read from off-chip data memory, used for both instruction access and load instructions.
• RdC. p[37] used to send a read request to memory.
• WrC. p[38] used to send a write request to memory.
• Mdone. p[39] used by the memory to signal that the operation is done.

• Read. To read a value at address X, drive Addr with the value X, and set RdC high. These signals must be stable during the non-overlap period. The data will be available on Din on the same cycle when Mdone is high.
• Write. To write value V at address X, drive Addr with the value X and Dout with V, and set WdC high. These signals must be stable during the non-overlap period. The data will be written to memory at the next period when either clock is high, and the signals being driven must be stable UNTIL Mdone goes high.

INORDER = a b c;
OUTORDER = p q r;
p = b|c;
q = !b&!c;
r = a&b;

To generate layout, use mpla -I -O -t /usr/local/cad/lib/mpla/norSUBM file.tt -o file, which will generate file.mag. The PLA layout may have some well plugs missing; you should put those in by hand.

As mentioned in class, the PLA layout WILL NOT LVS against the automatically generated CAST file.

• Your layout should fit in 3500x3500 lambda, since that will be the budget you get for lab 5.
• All layout except for PLA layout must pass LVS. To make your life easy, the simplest solution is to have a top level mag file that contains two subcells: one containing all the PLAs you used, and the other containing the rest of the layout. Wire up the datapath to the PLAs in the top-level cell. Finally, lvs -CE can be used for connectivity checking. This just checks variable names and looks for shorts/miswired signals. You should be able to check the entire top level design using this command.
• A simple state machine can be combined with simple logic to design this microcontroller. For instance, you can have a state machine that steps through states like "read instruction" and "read register operand" and "write results." The state information can then be combined with the instruction opcode to generate the necessary control signals for your entire datapath.
• Any write signal (register write, write control to the memory) cannot have a glitch on it; otherwise, there could be a data corruption problem. This can be ensured by using a 2-input AND gate with a clock as input to the gate (think about which clock should be fed into the gate, and when the other input to the gate is allowed to change in order to ensure that the output can never have a spurious 1).
• Use 2-phase non-overlapping clocks, and do not use flip-flops in your design.
• The complemented senses of the clocks are not available as inputs; therefore, you will have to generate them yourself.
• When simulating clocks in IRSIM, the clock definition will look like this:

  vector CLK p[0] p[1]
  clock CLK 00 10 00 01

• The lab number and the names of the group members and their CSL login ids.
• A picture of the complete layout for your processor.
• Cycle time estimate for your processor.
• The dimensions of the bounding rectangle for your layout in lambda. (i.e. your layout has area x lambda by y lambda), and the area of your layout in lambda square.

Electronic Submission. Use the CMS system to submit your files electronically. Create a .tar.gz file and submit that file. Make sure that the file contains a plain text README file that documents your submission. As in Lab 1, make sure that the .tar.gz file ONLY contains the files that you wrote; do not include any file that is generated by a tool (e.g., no .ext files, no .trace files, etc etc). Instructions on testing the lab should be contained in the README.