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Part 1. Implement an 8-bit register using the safe design
discussed in class in files reg.mag and
reg.cast. Make the register have two output ports
(you simply need to replicate the read part). The final register must
have two read control lines (for the two output ports) and one write
control line (for the one input port) that are common to each bit.
Create a test file test_reg.cast to test the register,
and an irsim script file test_reg.cmd
containing the tests for your design. The CAST definition for your
8-bit register must begin: define reg() (node[8] in, out0, out1;
node w,r0,r1) where in is the input bus,
out0 and out1 are the two output buses, and
w, r0 and r1 are the write
select and read select signals (for out0 and
out1 respectively).
Part 2. To support external inputs, we will include a "load"
unit that consists of an inverter followed by a controlled pass gate. The
production rules for one bit are:
_in&l->out- ~_in&~_l->out+
l->_l- ~l->_l+
in->_in- ~in->_in+
When l is high, the input in is copied to
the output out; when l is low, the output
is state-holding. Design an 8-bit load unit called
load.mag, with the production rules in
load.cast, and irsim test script
test_load.cmd. The CAST definition for the load unit must
begin: define load() (node[8] in, out; node l).
Part 3. To support external output, we will include a "read"
unit that consists of an inverter followed by a controlled pass gate. The
production rules for one bit are:
in&r->_out- ~in&~_r->_out+
r->_r- ~r->_r+
_out->out- ~_out->out+
When r is high, the input in is copied to
the output out; when r is low,
the output _out is state-holding, and keeps driving the previous value onto the output out. Design an 8-bit read unit called
read.mag, with the production rules in
read.cast, and irsim test script
test_read.cmd. The CAST definition for the read unit must
begin: define read() (node[8] in, out; node r).
Part 4. (For those who haven't done this already) Pitch-match
the layout from lab2 and lab3, so that the layout for each block can
be arrayed at the same bit pitch.
Part 5. Design a complete datapath that uses all the layout
from lab2 and this lab. The layout should be in
datapath.mag, and must lvs against the following
datapath.cast (given below).
- The datapath contains all the layout from lab2 and lab3. All the
layout MUST BE pitch matched, otherwise wiring it up will be
difficult. The layout should look like a sequence of vertical
columns, with each column corresponding to a major 8-bit block. The
order of the columns must be (from left to right, with cell identifier
in parentheses): load (
ld); fblock (fb);
load (rfb); oneshift (os); load
(ros); addsub (as); load (ras);
reg (reg0); reg (reg1); read
(rd).
- The output of each combinational block must be connected to the
input of the load block adjacent to it. That is, the output of
fb, os, and as must be
connected to the input of rfb, ros, and
ras respectively (see the CAST file below for details).
This effectively adds a tristate buffer on the output of each combinational
logic block.
- Finally, wire up the inputs and outputs using three buses.
- Each bit of the "a" input to each combinational block must be
wired together using a single, horizontal strip of either metal2 or
metal3 per bit (this is bus
rx in the CAST file). This
bus is also connected to the input of the rd (read)
block, and output port 0 of registers reg0 and
reg1.
- Each bit of the "b" input to each combinational block must be
wired together using a single, horizontal strip of either metal2 or
metal3 per bit (this is bus
ry in the CAST file). This
bus is also connected to output port 1 of registers reg0
and reg1.
- Each bit of the output of each load block (
rfb,
ros, ras and ld) must be wired
together using a single, horizontal strip of either metal2 or
metal3 per bit (this is bus wz in the CAST file). This
bus is also connected to the input port of registers reg0
and reg1.
A cartoon view of the layout and wiring is shown below:
Test your datapath CAST file by using the
test_datapath.cast file shown below and creating an
irsim script file test_datapath.cmd that performs the following operations:
- Loads constant values into registers;
- Reads the value of each regster using the external output;
- Adds two values and stores the result in a register;
- Shifts a value and stores the result in a register;
- Computes some logical function using the two registers as inputs
and stores the result in a register.
The link above provides a sample test script that should work with
your layout. Note that just because your layout works against this
script does not mean it is fully functional! The script is just a
starting point for testing, and you should modify it to add additional
test cases.
The file test_datapath.cast must be:
import "datapath.cast";
node[8] in, out;
node g0, g1, g2, g3;
node s, l, c;
node en_shift, en_addsub, en_fblock;
node w0,r00,r01,w1,r10,r11;
node ext_l, ext_r;
datapath d(in,out,g0,g1,g2,g3,en_fblock,s,l,en_shift,c,
en_addsub,w0,r00,r01,w1,r10,r11,ext_l,ext_r);
The datapath CAST file datapath.cast must be:
import "fblock.cast";
import "oneshift.cast";
import "addsub.cast";
import "reg.cast";
import "load.cast";
import "read.cast";
define datapath() (node[8] in, out; /* external IO */
node g0,g1,g2,g3; /* fblock control */
node en_fblock;
node s,l; /* shift control */
node en_shift;
node c; /* addsub control */
node en_addsub;
node w0,r00,r01; /* register control, register 0 */
node w1,r10,r11; /* register control, register 1 */
node ext_l; /* load control */
node ext_r /* read control */
)
{
/* data buses */
node[8] rx,ry,wz;
/* fblock, with a load interface on the output */
fblock fb(rx,ry,g0,g1,g2,g3);
load rfb(fb.out,wz,en_fblock);
/* shift, with a load interface on the output */
oneshift os(rx,s,l);
load ros(os.out,wz,en_shift);
/* addsub, with a load interface on the output */
addsub as(rx,ry,c);
load ras(as.out,wz,en_addsub);
/* two registers */
reg reg0(wz,rx,ry,w0,r00,r01);
reg reg1(wz,rx,ry,w1,r10,r11);
/* external load */
load ld(in,wz,ext_l);
/* read, can only read bus rx */
read rd(rx,out,ext_r);
}
Here is a summary of the files you will write in this lab. You can
use more (especially for subcells in your .mag file hierarchy).
reg.mag, reg.cast: register implementation
test_reg.cast, test_reg.cmd: register test
load.mag, load.cast: load block
test_load.cast, test_load.cmd: load test
read.mag, read.cast: read block
test_read.cast, test_read.cmd: read test
datapath.mag, datapath.cast: datapath
test_datapath.cast, test_datapath.cmd: datapath test
fblock.cast, fblock.mag: fblock (lab2)
oneshift.cast, oneshift.mag: shifter (lab2)
addsub.cast, addsub.mag: add/subtract (lab2)
The bold files are ones that are provided. A starting point for
test_datapath.cmd has also been provided.
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