Reminder: All layout in this class will use the magic technology file SCN3ME_SUBM.30, which can be specified on the command line by saying: magic -T SCN3ME_SUBM.30. You might want to alias magic to magic -T SCN3ME_SUBM.30 in your .cshrc.

Make sure you read the ENTIRE lab before starting.

In this lab, you will design and complete the physical design for restoring combinational logic implementations of three functions:

• A function block that can implement arbitrary Boolean functions of two variables;
• A ripple carry add/subtract circuit;
• An up/down shift-by-one circuit

Function block. The function block is used to compute any two-input Boolean function. It takes four control inputs g0, g1, g2 and g3.

The inputs to a single bit are Booleans a and b (in addition to the control inputs). If the two inputs ab are 00, the output is g0; if ab = 01, the output is g1; if ab = 10, the output is g2; if ab = 11, the output is g3.

The 8-bit function block is 8 copies of the one-bit block, with a common set of control inputs g0 through g3 shared by each bit. This structure can be used to compute any Boolean function of two variables, because g0 through g3 correspond to the truth-table entries for each input case.

Add/subtract. Design an 8-bit ripple carry adder with a single control input c that selects between addition and subtraction. Name the two inputs being added a and b.

Up/down shift by one. Design an 8-bit shift-by-one block. This block has one 8-bit input, control inputs s (shift/no shift) and l (left/right), and an 8-bit output. If s = 0, the output is the same as the input (no shift). If s = 1, then the output is either the input shifted left by one (if l = 1) or shifted right (logical) by one (if l = 0).

• define fblock() (node[8] a, b; node g0,g1,g2,g3; node[8] out) {..}
• define addsub() (node[8] a, b; node c; node[8] out) {..}
• define oneshift() (node[8] a; node s, l; node[8] out) {..}

The restoring logic for your design must be described using production rules. As an example, a two-input NAND gate would be described as follows:

define nand2() (node a, b, c)
{
  prs {
    ~a | ~b -> c+
     a &  b -> c-
  }
}

Create three test files test_fblock.cast, test_addsub.cast, and test_oneshift.cast that import the corresponding circuit definitions and create an instance for test purposes. The corresponding irsim test scripts should be named test_fblock.cmd, test_addsub.cmd and test_oneshift.cmd.

For each block of combinational logic, design a single one-bit cell that is vertically arrayed to form the actual eight bit logic block. IMPORTANT: The one-bit cells for fblock, addsub, oneshift should all be arrayed at the same vertical pitch.

You must also check that your physical layout implements the production rules in your CAST file by using the program lvs. For lvs to match your layout against production rules, the names you use for nodes in your layout MUST MATCH the names you use in your CAST file. In addition, cell ids must match the names used to instantiate defintions in CAST.

Suggestions:

• Each .mag file with transistors should have a corresponding .cast file.
• Check your leaf cells before you continue your layout.
• The CAST file hierarchy and layout hierarchy should match to keep matters simple.

• Run cit_ext2aspice file on file.ext. This generates file.aspice (and a few others).
• Write a test file file.cast that contains information about the technology and other simulation parameters. Run cflat -ADspice file.cast > file.asp to generate an aspice input file.
• Run aspice file, which saves the result of the simulation in file.trace.
• View the trace file using aplot

import "474/globals.cast";
import "474/aspice.cast";

asp {
.include "test.aspice";

.timemax=40e-9;

periodic(i) (2e-9,1.5e-9,1.6e-9);

/*
square(i) (5e-9,6e-9);
sethi(i) (5e-9,6e-9);
setlo(i) (8e-9,9e-9);
*/
}

After generating the .asp file, run aspice on the result and then use aplot filename to view the results of the simulation. The aplot commands can be obtained by saying help once aplot starts. The commands you will use most often are:

• add nodename adds the specified node to the list of nodes displayed in the graphical window.
• cross node value delay n can be used to measure when a node changes its value. After delay delay (in ns), aplot looks at the the times when node crosses voltage value, and reports the nth occurrence on the command line.

• rampup(n) (start,end); sets n to a voltage that goes from low to high over the interval [start,end].
• rampdn(n) (start,end); is similar to rampup, except that it sets the signal from high to low.

• Four inverters with W=4 and L=2 for both pfet and nfet with inputs _a, _b, _c, _d and outputs a, b, c, d respectively.
• Draw a single nfet with W=10,L=10, with both source and drain connected to GND! and gate labelled x.
• Draw a pseudo-NMOS NAND gate with output x (connected to the load nfet above) and with nfets having W=4 and L=2. The inputs to the gate are a, b, c, and d.
• For N=1, use W=4,L=4 for the pseudo-NMOS pullup transistor; for N=2, use W=4,L=2; for N=3, use W=6,L=2; for N=4, use W=8,L=2.

Here is a sample pseudo.cast file that might be useful for your simulation setup.

import "474/globals.cast";
import "474/aspice.cast";

asp {

.include "pseudo.aspice";
.timemax=40e-9;

cap(_a,GND) (1);
cap(_b,GND) (1);
cap(_c,GND) (1);
cap(_d,GND) (1);
sethi(_a) (1e-9,2e-9);
sethi(_b) (1e-9,2e-9);
sethi(_c) (1e-9,2e-9);
sethi(_d) (1e-9,2e-9);
setlo(_a) (10e-9,12e-9);
sethi(_a) (16e-9,18e-9);
}

• The lab number and the names of the group members and their CSL login ids.
• A picture of the complete layout for each of your (three) circuits (fblock, addsub, oneshift);
• The worst-case input to output delay for each of your circuits (use IRSIM on the extracted layout);
• The dimensions of the bounding rectangle for each circuit layout in lambda. (i.e. your layout has area x lambda by y lambda), and the area of your layout in lambda square.

Electronic Submission. Use the CMS system to submit your files electronically, as in Lab 1. Create a .tar.gz file and submit that file. Make sure that the file contains a plain text README file that documents your submission. As in Lab 1, make sure that the .tar.gz file ONLY contains the files that you wrote; do not include any file that is generated by a tool (e.g., no .ext files, no .trace files, etc etc). Instructions on testing the lab should be contained in the README.