Intel has increased it's domestic site forecast for recent graduate
hiring and we will be on campus Thursday March 4th to conduct Open
House Prescreen Interviews.  These prescreens will be conducted from 9
AM to 4 PM in the Yale/Princeton rooms of the Statler Hotel and are
for BS, MS that will be graduating in May - August 2004 and PhD that
will be graduating in 2004.  The primary disciplines we are looking
for are: 

  For BS: EE, ECE, ChE, CS (Minimum GPA 3.0)

  For MS and PhD: EE, ECE, ChE, CS, Mat Sci, MechE, Chemistry and
Physics.  

  The prescreen will last approximately 15 to 20 minutes per student
and are on a first come first served basis according to discipline.
Students may have to wait a short period of time for an interview
depending on student volume.  Students should bring a hard updated
(including current GPA) copy of their resume to the session.

Students seeking internships are welcome to stop by and drop off their
resume.  

Dress for these sessions is casual.  

 ** Candidates for our current domestic (US) positions must meet
Intel's citizenship requirement.  Candidates must have the permanent
right to work in the U.S. without any type of sponsorship.  Exceptions
may be made for PhD candidates with critical skills in an area of
demonstrated shortage in the US.  Although Intel does not have a
general policy that prohibits hiring students who have not yet
received green cards, Intel requires individuals from some countries
(including China, Iraq, Iran, Russia, Romania, Ukraine and others) to
have Export Licenses from the Department of Commerce prior to
beginning employment.  Individuals from these designated countries are
also restricted from accessing certain technology, based on Department
of Commerce regulations.  Intel's current available Domestic positions
are subject to Department of Commerce restrictions on exports and
technology  and are therefore not open to individuals from countries
that fall into these categories. **

**** Additionally, Intel's International Sites are looking for MS and
PhD students from those countries (Examples; India, China, Malaysia,
Russia) that would be interested in opportunities to return to their
home country.  Representatives for those sites will also be on campus
and available for screens. ****

• Quiz 6: The effect of connecting the clocks to their appropriate supply in the problem is to create a pseudo-NMOS implementation of the logic that was originally implemented using a clocked precharge PLA.
• Quiz 7: (1) A 2MxN array contains a log(2M) to 2M decoder that is used to select the appropriate line of the memory. The bit lines are longer, since 2M cells are connected to each bit line. Implementing the same storage with 2 MxN arrays requires smaller decoders (log(M) to M), but the word lines are longer because they now span 2N bits. The bit lines are shorter, because they only cover M bits. There is the additional overhead of a MUX at the output of the two MxN arrays to select the appropriate bit from each array using the left-over bit from the address (the one that is not used by the address decoder). (2) The dummy cell is used to provide a reference for a differential read operation. Introducing the dummy cell provides a reference value that is coupled to the word lines in the same way as the bit being read, thereby providing good noise immunity when combined with a differential sense amp.
• Quiz 8: The delays are d(0-⟩1)=tp(L/Wp); d(1-⟩0)=tn(L/Wn). The constraint is Wn+Wp=C. The problem is to minimize tp(L/Wp)+tn(L/Wn). Replacing Wn with C-Wp, taking derivatives, and setting the derivative to zero leads us to Wp/Wn=sqrt(tp/tn), which has the solution Wp=C*sqrt(tp)/(sqrt(tp)+sqrt(tn), and Wn=C*sqrt(tn)/(sqrt(tp)+sqrt(tn)).
• Quiz 9: The H-tree layout equalizes the lengths of the connections from the root of the H-tree to its leaves due to its symmetry, and therefore hopefully reduces clock skew between different points on the chip. The problem with an H-tree layout is that the leaves might not be equally loaded because clock load is not necessarily uniformly distributed on a chip. Also, depending on the coupling capacitances and the actual layout used for the H-tree (different metal layers, etc), the RC delay along the legs of the H-tree might not be equal either even if the end-point loads are identical.

• There is a template test file in ~rajit/test.cast. To try it out, copy test.cast to your own directory, run prs2sim test.cast (as usual), and then: cat ~rajit/test.x >> test.sim (i.e. append the contents of ~rajit/test.x to test.sim). Finally you need a mem.in file that contains a list of integers that correspond to the contents of memory starting from address 0. Instead of using irsim, use ~rajit/irsim.u474 to start the simulation. Once this works for you, put your CPU into test.cast at the appropriate place.
• To simulate your extracted layout, generate your sim file from your layout with the entire cpu (datapath + control) in one cell called "c". Run slashes2dots on the .sim/.al files (see lab3). Take the test.cast file as given and run prs2sim on that as well. Append test.sim to the sim file obtained from the layout, and append test.al to the .al file obtained from your layout. Finally, append ~rajit/test.x to the sim file as well and follow the procedure given above to simulate the final merged sim file.
• Highly recommended. Make a script for each procedure so you don't have to keep typing in the sequence of commands.

• Every cell that matches a cast definition should pass lvs by itself, including all staticizer checks, except
• The load unit and the register port connected to the busses should not have a staticizer on their output. This is because the output of multiple units will be shorted to each other (via the bus). If you did this, you will see strange errors like "weak feedback is not an inverter."
• Once the datapath is connected, the busses will need a staticizer, because none of the load units connected to it are staticized.

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