ECE696 - Contemporary Issues in Computer Architecture
Fall 2006
Time: Tuesday, Thursday 1:25-2:40pm
Place: Phillips 213 (note room change)
Credits: 4
Prerequisite: ECE475/CS416, or an equivalent course at another University, or permission of instructor
Instructor: Prof Dave Albonesi (Rhodes 333, albonesi at csl.cornell.edu)
Course requirements: Two exams, literature search report and presentation, and a course project
This advanced graduate course addresses current and emerging issues in computer architecture, with an emphasis on issues that arise from technology scaling. The objective is for the student to acquire a broad understanding of the technical literature, and experience in searching the literature and in simulation-based microarchitecture research, in order to engage in more in-depth research in the future.
The material is chosen to complement ECE575 (High Performance Processor Architecture) and ECE572 (Parallel Computer Architecture), although some degree of overlap is inevitable.
In lieu of a textbook, we will read and discuss technical papers from computer architecture conferences and journals. First, we will briefly cover the microarchitecture of dynamic superscalar microprocessors, the complexity of the major hardware structures, Simultaneous Multi-Threading (SMT), and Chip Multi-Processors (CMPs). Building on this fundamental knowledge, we will explore issues of power and reliability, and proposed microarchitectural solutions. Finally, research in the areas of adapting to application phase characteristics (adaptive processing) will be covered.
Topics
Microarchitecture of dynamic superscalar microprocessors
Complexity analysis of the major hardware structures
Microarchitecture of the Mips R10000 and Alpha 21264 microprocessors
Simultaneous Multi-Threading and Chip Multi-Processors
Power dissipation and power-aware computing
Soft and hard errors and microarchitecture-level solutions
Application phase tracking and adaptive processing
Exams
There will be two exams worth 20% each. There will not be a final exam.
Literature Search
You will perform an in-depth study of the technical literature in a particular area, write a report, and give a 20 minute presentation. Your ability as a public speaker will not be a factor; rather, your thoroughness in researching the particular area, and the quality of your report and presentation materials will determine your grade.
Project
One of the requirements is a research project (in an area that is
different from the literature search) where some particular problem is
modeled using simulation tools and solutions proposed and evaluated.
One of the lectures early in the course will be given by two PhD
students who will discuss the simulation infrastructure used for
research within CSL. That will give you a jump start on your project,
although you will need to spend many hours perusing the code, making
modifications, and debugging. I will give you some project
suggestions although you are free to suggest your own project. You
may work alone or with one partner.
Grading
Two exams: 20% each
Literature search and presentation: 30%
Project: 30%
Academic Integrity
Each student in this course is expected to abide by the Cornell University Code of Academic Integrity. Any work submitted by a student in this course for academic credit will be the student's own work. For this course, collaboration is permitted only for the course project, with the one partner listed in the project report cover sheet.
Papers Handed Out
The following papers are being covered in class and most can be obtained through IEEE Xplore:
The Microarchitecture of Superscalar Processors
Coming Challenges in Microarchitecture and Architecture
The Mips R10000 Superscalar Microprocessor
200MHz Superscalar RISC Processor Circuit Design Issues
The Alpha 21264 Microprocessor
A 600MHz Superscalar RISC Microprocessor with Out-Of-Order Execution
Design Tradeoffs in Stall-Control Circuits for 600MHz Instruction Queues
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Quantifying the Complexity of Superscalar Processors
Interconnect Scaling - The Real Limiter to High Performance ULSI
Understanding the Energy Efficiency of Simultaneous Multithreading
Temperature-Aware Microarchitecture: Extended Discussion and Results
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
CMP Design Space Exploration Subject to Physical Constraints
Heat and Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System
Techniques for Multicore Thermal Management: Classification and New Exploration
IBM Experiments in Soft Fails in Computer Electronics (1978-1994)
Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
The Soft Error Problem: An Architectural Perspective
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
ReStore: Symptom Based Soft Error Detection in Microprocessors
Microprocessor Sensitivity to Failures: Control vs. Execution and Combinational vs. Sequential Logic
Lifetime Reliability: Toward an Architectural Solution
The Impact of Technology Scaling on Lifetime Reliability
The Case for Lifetime Reliability-Aware Microprocessors
Exploiting Structural Duplication for Lifetime Reliability Enhancement
A Fault Tolerant Approach to Microprocessor Design
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
BulletProof: A Defect-Tolerant CMP switch Architecture
Ultra Low-Cost Defect Protection for Microprocessor Pipelines
Managing Multi-Configuration Hardware via Dynamic Working Set Analysis
Phase Tracking and Prediction
Comparing Program Phase Detection Techniques
Characterizing and Predicting Program Behavior and its Variability
Dynamically Tuning Processor Resources with Adaptive Processing
Energy Efficient Co-Adaptive Instruction Fetch and Issue
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Dynamically Trading Frequency for Complexity in a GALS Microprocessor